Flip-chip ball grid array (FCBGA) semiconductor package is incorporated with both the flip-chip and BGA structures, in which an active surface of at least one chip is electrically connected to a surface of a substrate via a plurality of conductive bumps, and a plurality of solder balls are formed on an opposite surface of the substrate to serve as input/output (I/O) connections. The FCBGA package does not require conventional bonding wires, and can be effectively reduced in size, as well as may reduce the resistance to improve the electrical performance thereof, thereby making the FCBGA package become a mainstream packaging technology for chips and electronic elements of the next generation.
In the flip-chip mounting technique, it is first to form a conductive trace layer on the active surface of the chip, wherein bond pads located at terminals of the conductive traces are used for external electrical connection. When the chip is to be electrically connected to the substrate, the above conductive bumps are formed on the bond pads of the chip, and then the active surface of the chip is turned upside down to be connected to a conductive trace layer on the substrate via the conductive bumps. The combined structure of the chip and substrate is subject to reflowing and underfilling processes, thus completing the flip-chip electrical connection.
The conductive bumps are conventionally made of tin (Sn)/lead (Pb). Since lead is toxic, lead-contained electronic products are becoming restricted in light of environmental protection, such that lead-free bumps are encouraged in development. Related prior arts include, for example, U.S. Pat. Nos. 6,231,691, 5,405,577 and 6,179,935, and Taiwanese Patent Nos. 528638, 527252 and 498009, which disclose the use of lead-free bumps such as pure Sn bumps, Sn—Ag bumps, Sn—Ag—Bi bumps, Sn—Ag—Cu bumps, or Sn—Ag—Cu—Bi bumps, among which Sn—Ag bumps and Sn—Ag—Cu bumps are primarily adopted in the industry.
However, Sn—Ag bumps do not contain copper (Cu) and thus has poorer structural strength than Sn—Ag—Cu bumps. During a stress reliability test in a thermal cycle, the test result shows that Sn—Ag bumps achieve lower reliability than Sn—Ag—Cu bumps, making Sn—Ag bumps less widely used than Sn—Ag—Cu bumps. On the contrary, fabrication of Sn—Ag—Cu bumps still renders a significant drawback that is difficult to be overcome. A conventional electroplating process has a restriction on metal ion exchange. Specifically, the electroplating process can be only used to form binary bumps but not ternary bumps such as Sn—Ag—Cu bumps. Accordingly, a conventional screen-printing process is usually employed to fabricate Sn—Ag—Cu bumps, in which however the content of copper would over raise a reflow temperature profile in a reflowing procedure, making the yield of the fabricated packages undesirably degraded. Therefore, the current lead-free bump technology is still not able to produce satisfactory lead-free bumps with good reliability and feasible fabrication processes.
FIGS. 1A to 1E show the procedural steps of the conventional screen-printing process for forming a Sn—Ag—Cu bump. Referring to FIG. 1A, a chip 10 is provided, and a passivation layer 11 is formed on an active surface 10a of the chip 10 with a bond pad 12 being exposed for external electrical connection. The passivation layer 11 is an insulating layer to provide a protection effect and a wetting function subsequent for a solder material. Referring to FIG. 1B, an under bump metallurgy (UBM) structure 14 is formed over the passivation layer 11 and covers the bond pad 12. The UBM structure 14 includes one or more metal layers such as chromium (Cr), nickel (Ni), titanium (Ti) and so on to increase wettability of the solder material, increase adhesion between the chip and the solder material, prevent oxidation, and serve as a metal diffusion barrier. Referring to FIG. 1C, a photoresist 16 is formed on the UBM structure 14 and subject to exposing and developing procedures to cover the position corresponding to the bond pad 12. Referring to FIG. 1D, an etching procedure is performed to remove the part of the UBM structure 14 not covering the bond pad 12 and the photoresist 16. Then referring to FIG. 1E, a dry film 17 is applied over the passivation layer 11 and has an opening to define a location for filling a lead-free solder material. Referring to FIG. 1F, a liquid Sn—Ag—Cu solder material 18 is filled in the opening of the dry film 17. Finally referring to FIG. 1G, when two reflowing procedures are carried out, the dry film 17 is removed, and a ball-shaped lead-free bump 19 is formed by surface tension generated during melting of the Sn—Ag—Cu solder material 18 in the reflowing procedures.
As discussed above, Sn—Ag bumps and Sn—Ag—Cu bumps, which are relatively more commonly used among the various lead-free bumps, both have undesirable drawbacks. Sn—Ag bumps not containing copper are weaker in structural strength and achieve lower reliability in the stress reliability test as compared to Sn—Ag—Cu bumps. On the other hand, Sn—Ag—Cu bumps containing copper lead to rise of the reflow temperature profile depending on the content of copper. This is because addition of copper would increase a eutectic point of the lead-free solder material. The more copper is added, the more the eutectic point rises. For example, in the case of the copper content more than 1%, the eutectic point of the lead-free solder material is increased to about 300° C.; on the contrary, a eutectic point of Sn/Pb 63/37 solder material is only about 183° C. As a result, during the first reflowing procedure, an operating temperature of the Sn—Ag—Cu solder material may be increased up to 300° C., and the dry film cannot sustain such a high temperature and becomes altered or deteriorated to be difficult for complete removal. The remaining residues of the dry film on the chip would degrade the adhesion reliability for example between an underfill material and the active surface of the chip.
Moreover, for a thermally liable material such as a laminate substrate that cannot tolerate a high temperature, the reflow temperature of 300° C. is so high to cause thermal stress generated between the chip and the substrate, which may lead to problems such as deformation or delamination of the chip and the substrate, deterioration of the electrical performance and cracking of the chip, and degradation of the yield.
Therefore, the problem to be solved here is to provide a process for forming a copper-contained lead-free bump on an electronic component under an appropriate reflow temperature profile.